1. Field of the Invention
The present invention relates to stacked dice packages and methods for fabricating the same. In particular, the present invention relates to the use of a flexible substrate for the fabrication of stacked dice packages.
2. State of the Art
Higher performance, reduced cost, increased miniaturization of integrated circuit components, and greater packaging densities of microelectronic devices are ongoing goals of the computer industry. One method of increasing the density of microelectronic device packages is to stack the individual microelectronic dice within the packages.
Various approaches have been taken in the fabrication of stacked dice packages. One approach is to simply attach a first microelectronic die (such as a microprocessor, a chipset, a memory device, an ASIC, and the like) to a carrier substrate (such as an interposer, a motherboard, a back surface of another microelectronic die, or the like). The first microelectronic die may be attached to the carrier substrate by its active surface (i.e., by flip chip attachment) or by its back surface with electrical contact made by wire bonds, as will be understood to those skilled in the art. A second microelectronic die is then stacked by its back surface on the first microelectronic die and secured by a layer of adhesive (and may include appropriate spacing devices). The second microelectronic die makes electrical contact with the carrier substrate through a plurality of bond wires extending between bond pads on an active surface of the second microelectronic die and land pads on the substrate. Although this approach appears simple, the fabrication process is relatively complex and this approach requires lands pads on the carrier substrate, which takes up valuable xe2x80x9creal estatexe2x80x9d thereon.
Another approach includes the use of a flexible substrate to route electrical traces from the second microelectronic die to a position between the first microelectronic die and the substrate to make electrical contact with the carrier substrate. FIG. 10 shows such an arrangement, wherein a first microelectronic die 202 and a second microelectronic die 204 are attached to and in electrical contact with a first surface 208 of a flexible substrate 206 through attachment interconnects 212 and 214, respectively. An encapsulant material 216 is dispersed under and proximate each of the first microelectronic die 202 and the second microelectronic die 204.
The flexible substrate 206 includes conductive traces (not shown) disposed therein, thereon, and/or therethrough which make contact with an array 222 of external interconnects 224 (such as solder balls) disposed on a second surface 226 of the flexible substrate 206 proximate the first microelectronic die 202. Thus, both the first microelectronic die 202 and the second microelectronic die 204 have external interconnects 224 within the array 222. The flexible substrate 206 is bent such that a back surface 232 of the first microelectronic die 202 can be attached to a back surface 234 of the second microelectronic die 204 with a layer of adhesive 236. The external interconnects 224 are attached to a carrier substrate 238 using a C4 (controlled collapse chip connect) process.
Although such an approach results in an effective stacked package, it is not conducive to having microelectronic dice that are mismatched in size or height, or mismatched between microelectronic die that are encapsulated and those that are not, as the first microelectronic die back surface 232 and second microelectronic die back surface 234 must provide adequate surfaces for attachment to one another. These deficiencies greatly reduce the utility of such stacked packages.
Furthermore, passivation damage may occur with such stacked packages. Passivation damage is a defect of microelectronic die where the surface coating of the circuit was torn, scratched or pierced by any material exposing the microelectronic die traces or even damaging the integrated circuitry resulting in an electrical circuit xe2x80x9copenxe2x80x9d, as will be understood by those skilled in the art. It is commonly induced in microelectronic die attach processing with relative sensitive adhesive material, high bonding force requirement, and exposure to environment with lots of particles floating around. Boneline thickness control is also a problem on thin microelectronic die processing using paste adhesive. Microelectronic die level warpage is the effect of thinning the microelectronic die (e.g., silicon) that makes mechanical stresses on the wafer becomes visible after being grinded. It also becomes significant enough to affects the straightness of the adhesive bondline thickness. Special flattening process is required to resolve the issue.
Therefore, it would be advantageous to develop a stacked package that is conducive to the use of a variety of microelectronic die sizes and types and that reduces the potential for passivation damage.